1. Field of the Invention
The present invention generally relates to methods for describing circuit designs using behavioral descriptions and more particularly relates to methods for selectively providing modularity and/or hierarchy to a behavioral description.
2. Description of the Prior Art
The design process for all integrated circuits is composed of several discrete operations. Initially, the proposed functionality for a circuit is analyzed by one or more chip designers. These designers define the logical components of the circuit and their interactions by specifying the logic design using design capture tools. These design capture tools are commonly implemented in software executing on an engineering workstation, with well-known input devices being used to receive design information from the chip designer, and output devices, such as computer displays, being used to provide visual feedback of the design to the designer as it is being constructed. Such software is typically implemented as part of an electronic design automation (EDA) system. Specifically, the design entry operation involves generating a description of the logic design to be implemented on the circuit chip in an appropriate machine-readable form.
A common method for specifying the integrated circuit design is the use of hardware description languages. This method allows a circuit designer to specify the circuit at the register transfer level (also known as a xe2x80x9cbehavior descriptionxe2x80x9d). Using this method, the circuit is defined in small building blocks. Encoding the design in a hardware description language (HDL) is a major design entry technique used to specify modern integrated circuits. Hardware description languages are specifically developed to aid a designer in describing a circuit. These languages often contain specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way.
It is often desirable to employ hierarchial design techniques to describe the appropriate selection and interconnection of logic and/or memory devices which will enable the chip to perform the desired function. Hierarchical design techniques often involve describing the chip""s functionality at various levels of abstraction, ranging from the most general function performed by the chip to the precise functions performed by each logic and/or memory element on the chip.
An efficient way to store a hierarchical circuit design is to provide modularity to the circuit design database. Modularity is a term used to describe the concept of representing identical functions in the circuit design with multiple instances of a common component or module. For example, a common adder bit slice may be described using a behavioral language, and the resulting behavioral description may be stored as an adder bit slice module in a design library. When an N-bit adder is desired, the circuit designer may instantiate xe2x80x9cNxe2x80x9d adder bit slice modules. Each adder bit slice instance within the circuit design may reference the behavioral description for the common adder bit slice module. Providing modularity is separate from providing hierarchy to a circuit design, as modularity may be provided without providing hierarchy, and visa versa. However, typically modularity and hierarchy are provided together.
A non-modular circuit design database must typically describe each instance separately and independently. That is, and continuing with the above example, for each of the N-bit adder bit slices, a non-modular circuit design database may include xe2x80x9cNxe2x80x9d copies of the behavioral description for the adder bit slice module, one for each adder bit slice instance.
A modular database has a number of advantages over a non-modular database. First, the amount of data that must be stored to describe a circuit design using a non-modular database structure may be significantly higher because each instance must be independently described and stored. In a modular database structure, the description for each identical instance is typically shared.
In addition to the above, and because the description for each identical instance is typically shared, it is easier to ensure that the most current version of the corresponding behavioral description for a particular module or component is provided throughout the circuit design. For example, in a modular database, a circuit designer may modify the behavioral description for a particular shared module. That change may then be reflected in each instance of that module because the description therefor is shared. In a non-modular database, the circuit designer typically must modify the description for each instance of the module. As can readily be seen, the modification of modules in a non-modular database may be error prone and tedious.
Another advantage of providing modularity to a circuit design is that the time required to synthesize a behavioral description into a corresponding detailed description may be reduced. That is, because a number of instances may share the same behavioral description, the common behavioral description may be synthesized once, and the resulting detailed description may be shared. This is particularly useful when the common behavioral description does not include any internal nets or variables that will conflict with other instances of the same module (for example, an AND2 gate). It is recognized that the interface section of each instance of the module may have to be processed to define unique interconnect of each instance to the overall circuit design. However, this may still reduce the time required to synthesize the overall behavioral description of the circuit design. In contrast, and in non-modular databases, the behavioral description for each identical module must be independently synthesized into a number of corresponding detailed descriptions.
A number of modular behavioral description languages currently exist, including the VHSIC Hardware Description Language (VHDL). VHDL has a number of constructs, including the component construct, which allow components to be instantiated within a circuit design. Each instantiation of a component references a common behavioral description. Each instantiation of a component is essentially a procedural call to the behavioral description of the component, and thus does not incorporate the behavioral description of the components into the behavioral description of the overall circuit design.
Many hardware description languages do not allow true modularity. For example, the UDSL hardware description language available from UNISYS Corporation is essentially a non-modular hardware description language. In addition, some behavioral simulation and logic synthesis tools cannot directly read and operate on modular hardware descriptions.
It should be recognized that many design tools are typically used during the design of an integrated circuit including high level behavioral simulator tools, detailed description simulator tools, synthesis tools, logic optimizer tools, manual placement or floorplanning tools, place and route tools and verification tools. Because some but not all design tools are compatible with modular hardware description languages, it would be desirable to use both modular and non-modular compatible tools, depending on the availability and overall effectiveness of the tools. That is, it would be desirable to provide a non-modular behavioral description to those tools that are available but cannot handle modularity. Likewise, it would be desirable to provide a modular behavioral description to those tools that are available and can handle modularity. Thus, it would be advantageous to provide a behavioral description that can be selectively expanded to include modularity therein, depending on the design tools that are selected for use in the design process.
Regardless of whether a modular or non-modular behavioral language is used, the manual placement of selected cells and modules within a circuit design can be a major task. Until recently, much of the cell placement function was performed using automatic placement tools. However, because many modern integrated circuits are pushing the limits of density and performance, circuit designers are often forced to manually place a number of critical cells within the design. It is known that manual placement often provides a more optimal placement solution than an automatic placement tool.
The manual placement of modules and cells within a circuit design is particularly tedious because some synthesis tools remove the modularity and/or hierarchy that may be provided in the behavior description. Thus, the detailed description provided by the synthesis tool can typically be non-modular. Even if modularity is provided, typical manual placement tools may not recognize the modularity provided in the detailed description. Thus, when placing identical instances of a module, each instance (including those cells or modules contained within each instance) must be placed separately. Thus, and continuing with the above adder example, a circuit designer may manually place all cells and modules within a particular instance of an adder bit slice. To place another adder bit slice, however, the circuit designer may have to repeat the same placement for all cells and modules within all other instances of the adder bit slices. This makes the manual placement of many circuit designs tedious and error prone.
The present invention overcomes many of the disadvantages of the prior art by providing a method and apparatus for selectively providing modularity to a behavioral description of a circuit design. This is accomplished by providing a template for a selected portion of the circuit design. The template includes a template call and a corresponding template behavioral description. The template is instantiated in the behavioral description of the circuit design by including the template call therein. The behavioral description may then be expanded using an expander preprocessor. The expander preprocessor incorporates the behavioral description of the template into the behavioral description of the circuit design, and provides template markers to identify the location of the template. For those tools that cannot directly read hierarchical behavioral descriptions, the template markers are ignored. For those tools that can directly read hierarchical behavioral descriptions, the template markers are interpreted, and a hierarchical module corresponding to the template is provided.
When prompted, the expander preprocessor also can create a dummy module when it encounters the first expansion of a given template. This dummy module may be used by a logic synthesizer to generate a common placement module for inclusion in a placement database. During manual placement, each instance of a given template may reference the common placement module, and the manual placement tool may provide a mechanism for sharing the placement information between selected instances. Using this approach, a circuit designer may place the internal cells of a module using the manual placement tool. Because other instances of that module may share the same placement information, the internal cells of the other instances may be automatically placed by simply referencing the common placement information. This may significantly reduce the time required to place a circuit design.
In a preferred embodiment, a number of template calls are provided in a behavioral description of a circuit design. Each template call corresponds to an instantiation of a module or cell, and references a corresponding template behavioral description. Multiple instances of a particular module may reference the same template behavioral description.
The template call includes a template name, an instance name, a number of formal parameters, and the input and output nets that the template is connected to within the overall behavioral description of the circuit design. The template call is preceded by a #expand identifier, and is contained within comment delimiters for identification purposes by the expander preprocessor.
The expander preprocessor replaces the template calls with the actual text of the corresponding template behavioral description. In addition, the expander preprocessor replaces, by text substitution, the formal parameters and input/output net names within the template behavioral description with the template parameters specified in the template call. The expander preprocessor may also perform arithmetic or boolean operations to determine an appropriate value for the format parameters and/or input/output names. This effectively customizes the template behavioral description for each instantiation of the template. Finally, the expander preprocessor may provide template markers to mark the location of each template, which may be used by other tools as descried below.
When modularity and/or hierarchy is not desired, for example when a circuit designer wishes to provide the overall behavioral description of the circuit design to a tool such as an EDDE logic simulator which cannot handle modular behavioral descriptions, the expander preprocessor ignores the template markers and provides an essentially flat behavioral description. When modularity and/or hierarchy is desired, for example when a circuit designer wishes to provide the overall behavioral description of the circuit design to a tool such as a logic synthesizer that can handle modular behavioral descriptions, the expander preprocessor interprets the template markers, and a hierarchical module corresponding to the template is inserted.
In addition to the above, when prompted the expander preprocessor may generate a common template module when it encounters a first occurrence of a given template. The common template module may then be used by, for example the logic synthesizer, to provide a synthesized common template module that can be referenced by all instantiations of the given template. The logic synthesizer may synthesize the common template module, but may skip over all other instances of a given template, and simply reference the template calls to define the interconnect for each instance. This may be particularly useful when the resulting detailed description is provided to a manual placement tool, where each instance of a template may reference the same placement information of the common template module. As described above, this may significantly reduce the time required to perform manual placement of a circuit design.